1. Field Of The Invention
The present invention relates to a direct current power supply device which generates an alarm signal when a power failure occurs in an alternating current power supply connected to an input side thereof.
2. Description Of The Prior Art
FIG. 4 is a block diagram illustrating a direct current (DC) power supply in the prior art. Referring to that Figure, an alternating current (AC) power supply 1 is connected to an AC/DC converter 2 at input terminals 6 and 7. The AC/DC converter is conventionally used for converting an alternating current provided by the AC power supply 1 into a direct current at output terminals 8 and 9. A power failure detector circuit 3 is connected across the input terminals 6 and 7 and is operative to detect the absence of a signal across those terminals, indicating a power failure of the AC power supply. If a power failure is detected, a detector signal 4 is output by the power failure detector circuit 3. The detector signal 4 is provided directly to an output terminal 13 and to a delay circuit 5, which delivers a delayed detector signal 12a to an input of OR gate 12 a predetermined period of time after the power failure detector signal 4 has occurred. A load 10 is connected across the output terminals 8 and 9 of the AC/DC converter 2, as is a DC low voltage output detector circuit 11 for detecting a reduction of an output voltage of the AC/DC converter 2 below a threshold value and generating an alarm signal 12b. Alarm signal 12b forms a second input to OR circuit 12, which provides an output signal 12c to output terminal 14 whenever there is either an output of the delay circuit 5 or an output of the DC output low voltage detector circuit 11. Signal 12c is used as a reset signal for starting a power-failure processing operation of the electronic circuit connected as the load 10.
Referring now to the operation timing charts in FIGS. 5 and 6, both charts illustrate operations of the DC power supply device of the prior art. FIG. 5 shows operation timing at the occurrence of a power failure in the AC power supply 1 when the current flowing in the load 10 is small (hereinafter referred to as "under light load"). In FIG. 5, waveform A illustrates a voltage waveform output by the AC power supply 1, initially during normal operation and then after the occurrence of a power failure in the AC power supply 1, at a time identified by time point 102. Waveform C illustrates the waveform output from the power failure detector signal 4, appearing at terminal 13, which is inactive before a power failure occurs in the AC power supply 1 and is active after a time point 104, which occurs a time period T1 after the power failure has occurred at time point 102. The delay T1 occurs because of the inherent signal delay provided by components in detector circuit 3. Waveform D illustrates the waveform of the reset signal 12c, appearing at terminal 14. This signal is inactive until time point 106, which occurs a preset time delay T2 after the occurrence of time point 104, and is active after the time point 106. For all practical purposes, T1 and T2 are fixed periods of time. Waveform B illustrates the output voltage waveform of the AC/DC converter 2. In the case illustrated in FIG. 5, since the current flowing in the load 10 is small, the DC output voltage of the AC/DC converter 2 is maintained by the charge stored in a capacitor (not illustrated) provided inside the AC/DC converter 2 and is not immediately reduced. The reset signal D at the time point 106 actually occurs before the DC output drops. The reduction is first identifiable later, when a voltage threshold is crossed at time point 108, after a time period T3 has elapsed. Thus, the detector circuit 11 first detects a reduction of the output voltage of the AC/DC converter 2 below the threshold level well after the power failure occurs. This delayed detection creates a problem when there is an instantaneous power failure, and the power returns to normal prior to an actual drop in DC output voltage. In such case, there is a possibility that a reset signal will be generated even if there is no existing problem due to the return of the power supply to normal.
FIG. 6 illustrates operation timing at the occurrence of a power failure in the AC power supply 1 when the current flowing in the load 10 is large (hereinafter referred to as "under heavy load"). The signals illustrated by waveforms A and C of FIG. 5 remain the same in this Figure. However, since the current flowing in the load 10 is large, the charge stored in the capacitor (not illustrated) provided inside the AC/DC converter 2 is immediately consumed. Thus, as illustrated in waveform B, the DC voltage at output terminals 8 and 9 is reduced and low voltage detector circuit 11 detects a reduction of the output voltage of the AC/DC converter 2 below a threshold value at a time point 109, prior to the time point 106 in FIG. 5. Application of this input to OR gate 12, prior to the input from delay circuit 5, causes the reset signal 12c to become active early. The accuracy of the DC output voltage detector circuit 11 is often insufficient, and in a conventional DC power supply device which produces a large range of output voltages at terminals 8 and 9 of the AC/DC converter 2, even a normal voltage may activate the low DC output voltage detector circuit 11 and be detected as a fault. In order to prevent a normal voltage from being detected as a fault, the prior art sets the fault detection threshold voltage level of the DC voltage detector circuit 11 at a value lower than the nominal operating voltage level of a circuit element used in an electronic circuit connected to the load. Because the threshold under these conditions is set quite low, the operation of the electronic circuit lacks reliability when a power failure actually does occur.
The DC power supply device of the prior art, constructed as described above, has several disadvantages. As noted previously, when the DC power supply device is employed under light load, an unnecessary alarm signal may be generated at the occurrence of an instantaneous power failure which returns to normal prior to the occurrence of time point 108, when the output voltage of the AC/DC converter 2 is reduced below the threshold value. A further disadvantage is seen when the DC power supply device is used under heavy load and the threshold voltage is set quite low. In that case, an alarm signal is generated only after the output voltage has been reduced below the operational voltage of the electronic circuit connected to the load.